Technology Lead – Memory Layout

About the role

Infosys is seeking a Technology Lead to drive memory layout design for its Memory Team in Burnaby, BC. The role focuses on creating high‑performance memory leaf‑cell libraries and integrating them with registers and memory arrays across advanced process nodes.

Key responsibilities

• Develop custom memory layout and leaf‑cell libraries from concept to tape‑out.
• Collaborate with circuit and physical design teams to translate schematics into optimal layouts.
• Perform physical verification (DRC, LVS, ERC, boundary checks) and debug layout issues.
• Ensure designs meet FinFET 3nm/5nm technology constraints and performance targets.
• Maintain documentation and provide technical guidance to junior engineers.

Required profile

• Bachelor’s degree in Electrical Engineering, Computer Engineering or related field (or equivalent experience).
• Minimum 5 years of experience in compiler or custom memory layout design.
• Hands‑on experience with 3nm/5nm process nodes and FinFET technology.
• Ability to work onsite in Burnaby and travel within Canada as needed.

Required skills

• Custom memory layout and leaf‑cell library design.
• FinFET technology knowledge and DRC limitations.
• Physical verification flow: DRC, LVS, ERC, boundary conditions.
• Cadence Virtuoso layout editor.
• Calibre verification tools.