FPGA Engineer

About the role

The FPGA Engineer will create and verify real‑time processing and control logic that sits directly next to Q‑Block’s quantum hardware. This role spans RTL design, high‑speed interfaces, DSP pipelines, and sub‑microsecond timing across multi‑channel systems.

Key responsibilities

• Design, implement, simulate, and verify RTL modules in VHDL or Verilog for real‑time control and data acquisition.
• Develop high‑speed digital interfaces to ADCs, DACs, DDS synthesizers, and multi‑gigabit serial transceivers.
• Implement deterministic timing and synchronization logic for multi‑node hardware with sub‑microsecond precision.
• Create and maintain FPGA build flows, constraint files, and synthesis scripts for target platforms.
• Perform on‑hardware debugging using logic analyzers, oscilloscopes, and embedded instrumentation (ILA, SignalTap).

Required profile

• Bachelor’s degree in Electrical, Computer, Engineering Physics, Physics or related field (Master’s a plus).
• 4+ years of professional FPGA design and verification experience.
• Hands‑on experience with Xilinx Vivado, Intel Quartus or Lattice toolchains and timing closure.
• Proficiency with laboratory instruments such as oscilloscopes, logic analyzers and signal generators.

Required skills

• VHDL, Verilog, SystemVerilog.
• Xilinx Vivado, Intel Quartus, Lattice toolchains.
• High‑speed digital design (clock domain crossing, metastability mitigation, pipelining).
• JESD204B/C, LVDS, multi‑gigabit serial interfaces.
• DSP implementation (FIR/IIR filters, NCO, CORDIC, channelizers).
• Xilinx Zynq / Zynq UltraScale+ platforms and AXI integration.
• UVM, cocotb, Tcl and Python for verification and flow automation.

What we offer

• Competitive salary range $105,000 – $145,000 CAD per year.
• Extended health care including dental and vision.
• Life insurance coverage.
• Equal‑opportunity workplace with accommodations available.