Technology Lead – Analog Layout

About the role

Infosys is seeking a Technology Lead to drive analog and RF layout development for advanced semiconductor blocks. You will collaborate with layout engineers and RF designers to create transistor‑level layouts for circuits such as bandgap references, ADC/DAC, mixers, power amplifiers, PLLs, and LNAs.

Key responsibilities

• Develop detailed transistor‑level layouts for analog and RF circuit blocks.
• Ensure layout compliance with verification flows including extraction, DRC, LVS, and DFM.
• Review power/ground routing, electromigration, signal path integrity, and device matching.
• Coordinate with designers to meet performance targets and design rules.
• Provide documentation and support for layout sign‑off.

Required profile

• Bachelor’s degree (or foreign equivalent) in a relevant engineering discipline.
• Minimum 4 years of IT/semiconductor experience, preferably in analog/RF layout.
• Located within commuting distance of Vancouver, BC, or willing to relocate.
• Authorized to work in Canada without employer‑based visa sponsorship.

Required skills

• FinFET technology experience (N5/N3/N2 or more advanced).
• Custom RF/analog layout for deep sub‑micron CMOS processes.
• Proficiency with CALIBRE DRC, ERC, and LVS interpretation.
• Knowledge of Cadence Virtuoso Layout XL.
• Device matching, parasitic minimization, RF shielding, and high‑frequency routing techniques.
• Understanding of RC delay, electromigration, signal coupling, guard rings, DNW, PN junctions, LOD, and WPE effects.

What we offer

• Estimated annual compensation: CAD 90,450 – 136,500.